Ingénieur Optimisation et Inférence IA Edge.

Job Description

Responsible for deploying cutting-edge computer vision, speech, and multimodal neural network models onto edge and on-device hardware platforms. Through model compression, quantization, pruning, operator fusion, and microarchitectural tuning, you will deliver ultra-low latency, minimal memory footprint, and high-efficiency inference on resource-constrained devices.

Key Responsibilities

• Drive on-device quantization and compression (INT8, INT4, mixed-precision) for SLMs, speech models (Whisper/Conformer), and vision backbones
• Adapt and optimize inference pipelines across heterogeneous silicon targets (Rockchip RKNN, ESP-NN, TensorRT, TFLite-Micro, ONNX Runtime, TVM)
• Optimize on-chip SRAM/DRAM memory layout, cache locality, and bandwidth utilization under strict MCU/MPU memory limits
• Build automated on-device benchmarking pipelines to evaluate latency, accuracy degradation, and energy efficiency (TOPS/Watt)
• Partner with algorithm researchers and embedded firmware teams to port research prototypes into production-grade C/C++ runtime libraries

Requirements

• Master's degree (or equivalent experience) in Computer Science, AI, Software Engineering, or Microelectronics
• 3+ years of hands-on experience in on-device AI model optimization, custom operator development, or embedded acceleration
• Fluent in C/C++ and Python, with a strong grasp of computer architecture and SIMD intrinsics (ARM NEON, AVX)
• Solid mastery of PyTorch; proficient in TensorRT, ONNX Runtime, TFLite, RKNN, or OpenVINO
• In-depth understanding of PTQ (Post-Training Quantization) and QAT (Quantization-Aware Training)
• Hands-on experience with ARM Cortex-M/A microcontrollers or dedicated NPUs/DSPs is a strong plus